Cisco New Grad 2023 | Batch 2023 | Fresher | Engineering

Cisco invites latest engineering graduates or pursuing students for off campus hiring drive under the New Grad Program for the position on ASIC Engineer. It is full time permanent role job. Working style is work from office. A location of job is Bangalore, India. If candidate meet the required eligible criteria those can check out the details of role and eligibility criteria and apply from the given below link. Lets fill it now.

About Company

cisco new grad

Cisco Systems, Inc., abbreviated as Cisco, is a multinational digital communications technology conglomerate headquartered in San Jose, California. Cisco designs, manufactures, and sells networking hardware, software, telecom equipment, and other high-tech services and products. focuses on specific technology markets such as the Internet of Things (IoT), domain security, videoconferencing, and energy management, with leading products such as Webex, OpenDNS, Jabber, Duo Security, and Jasper. Cisco is one of the world’s largest technology companies, ranking 74 on the Fortune 100 and employing nearly 80,000 people.

Position Name – ASIC Engineer

Eligibility for Cisco New Grad 2023

  • Students passing out in 2023 and Pursuing Bachelor / Master degree in Electronics Engineering /Micro Electronics/VLSI.
  • Ability to manage multiple tasks and work toward long-term goals.
  • Solid understanding of engineering fundamentals and technical problem-solving skills.
  • Experience in establishing and sustaining strong relationships with the extended team.
  • Excellent communication skills (verbal and written).
  • Knowledge in Hardware design, the test/verification environment designed using an object-oriented framework designed in using UVM so you will use knowledge from your programming courses that include advance data structures, algorithms, and design patterns as well as languages such as SystemVerilog HDL / C / C++ / Python
  • You will aid in the architecture of the test environments which include developing constrained random stimulus generators, automated response checkers, and advanced configuration and programming API components using UVM.
  • Some of these components are reused across the entire phase of the project from module, chip and system level verification on Linux based Verilog simulators.
  • Problem solving skills and out-of-the-box thinking to create area and power efficient hardware designs as well as reusable UVM classes for the verification and simulation environments.
  • Physical Implementation of blocks, clock trees, Static Timing Analysis, DFT, Logic Equivalence Checks are part of the Physical Design specialist profile.
  • Writing thorough and detailed specifications and test plans as well as oral descriptions will enable your ideas and concepts to be reviewed and accepted by other team members.

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